1. Field of the Invention
Embodiments of the present invention relate to a nonvolatile memory (NVM) device, which is a byte-operational nonvolatile semiconductor memory device.
2. Description of the Related Art
Nonvolatile semiconductor memory devices are able to retain data even when power is not supplied. Nonvolatile semiconductor memory devices may be classified into mask ROMs, EPROMs, and EEPROMs. Bulk-erasable EEPROMs are often called flash memories or flash EEPROMs. Each 1-bit memory cell of an EEPROM may include a pair of transistors, a bit select transistor, and a memory transistor. A bit select transistor is for selecting a bit memory cell. A memory transistor is for storing data. An EEPROM memory transistor operates utilizing a Fowler-Nordheim tunneling (F-N tunneling) mechanism when programming data or erasing data. Bulk-erasable flash memory devices are able to erase groups of data stored in memory cells at one time. Bulk-erasable flash memory devices may be classified as block-erasable, sector-erasable, or page-erasable flash memory devices in accordance with the amount of data erasable at one time. Each 1-bit memory cell of a bulk-erasable flash memory device may include a single memory transistor.
Flash memory devices may be categorized as either NAND-type devices or NOR-type devices according to the connection state of memory cells. Although a NAND-type flash memory can rapidly program and erase data, NAND-type flash memory are not capable of random access. However, a NOR-type flash memory is capable of random access, but is slow at programming and erasing data. NAND-type flash memory and NOR-type flash memory differ in operating mechanisms. During erase operations, both NAND-type and NOR-type flash memories utilize a F-N tunneling phenomenon. However, during program operations, while the NAND-type flash memory operates using F-N tunneling, the NOR-type flash memory operates using a channel hot electron injection (CHEI) phenomenon. According to the CHEI phenomenon, a difference in electrical potential between a source and a drain causes carriers to flow, while a relatively high or low voltage is applied to a gate electrode. Accordingly, electrons or holes are injected into or trapped in a floating gate or an insulating layer (e.g. a nitride layer). Since trapping of electrons or holes occurs adjacent to a source, this method is often referred to as source side injection (SSI).
Nonvolatile memory devices are used in a variety of applications and new applications continue to be aggressively developed. For example, nonvolatile memory devices are employed in embedded memories of memory cards. Memory cards (e.g. flash memories) are popular as storage media in portable digital electronic devices, such as mobile phones, set-top boxes, MP3 players, digital cameras, camcorders, and PDAs.
Usefulness of nonvolatile memory devices may be increased if they operate to erase data one byte at a time. An example of byte-operational nonvolatile memory devices is disclosed in U.S. patent application Ser. No. 10/022,314 (U.S. Patent Application Publication No. 2002/0114185 A1). FIG. 1 is a description of a byte-operational nonvolatile memory device based on U.S. patent application Ser. No. 10/022,314. FIG. 1 is a diagram of a memory cell equivalent circuit of a byte-operational nonvolatile semiconductor memory device. In FIG. 1, a “byte memory cell” (i.e. an 8-bit unit memory cell) is illustrated inside the dotted lines.
In FIG. 1, the byte memory cell comprises a memory cell block and a byte-operational block. The memory cell block includes 8 single-bit memory cells. Each single-bit memory cell includes a pair of transistors connected in series. The pair of transistors include the memory transistor 110 and the bit select transistor 120. The memory transistor 110 has a gate electrode structure of a stacked floating gate type, which operates through F-N tunneling in both programming and erasing operations. The byte-operational block also includes the byte select transistor 130. Source S of the bit select transistor 120 is connected to drain D of the memory transistor 110. Drain D of the bit select transistor 120 is connected to a bit line (e.g. BLmo). Each bit line is connected in parallel to a memory transistor arrayed in another byte memory cell in the same column. Drain D of the byte select transistor 130 is connected to an mth program line GSLm. Source S of the byte select transistor 130 is connected to the gate G of the memory transistor 110. Gates G of the bit select transistors 120 and the byte select transistor 130 are commonly connected to an nth word line WLn. The nth word line WLn is connected to both the bit select transistor 120 and the byte select transistor 130 in another byte memory cell arrayed in the same row.
A nonvolatile semiconductor memory device of FIG. 1 has specific characteristics. For instance, since the byte select transistor 130 is capable of selecting single-bit memory cells in groups of a byte, it is also possible to erase data stored in the single-bit memory cells in groups of a byte. Also, in the nonvolatile memory device of FIG. 1, voltage transmitted through the byte select transistor 130 is applied to gate G of the memory transistor 110 in programming, erasing, and reading. Accordingly, voltage characteristics of source S have a great influence on operating characteristics of the semiconductor memory device, whereas the amount of current flowing through a channel of the byte select transistor 130 is not an important factor. Because current is not an important factor, the byte select transistor 130 can be disposed on the side of each byte memory cell. Accordingly, it is not necessary for the channel width of the byte select transistor 130 to have a large channel width.